Un quartiere sperimentale a Sant'Erasmo. Studi per una progettazione integrata

Il volume nasce dagli sforzi di docenti e studenti del laboratorio integrato di Progettazione urbanistica del corso di laurea magistrale in Architettura dell\u2019Universit\ue0 degli Studi di Udine, nell\u2019anno accademico 2015\u20132016. L\u2019opera analizza la sperimentazione di nuove forme di citt\ue0 umanistica che, ribaltando il processo pianificatorio del Novecento, possano individuare buone pratiche per la pianificazione della citt\ue0 attraverso la progettazione puntuale e rappresenta il tentativo di far crescere negli studenti l\u2019attenzione per lo spazio minuto della citt\ue0 consolidata. Cosa c\u2019\ue8 di meglio dello spazio concluso di un\u2019isola della Laguna di Venezia per costringere a ripensare le forme contemporanee per la nuova citt\ue0 compatta? Il modello potrebbe essere esportato per contrastare il consumo di suolo e per migliorare i rapporti sociali di vicinato \u2014 tornando a interpretare gli spazi \u201call\u2019italiana\u201d per un\u2019architettura contemporanea \u2014 attraverso una pianificazione semplice basata su una progettazione complessa

Performance and reliability comparison of 1T-1R RRAM arrays with amorphous and polycrystalline HfO2

In this work, a comparison between 1T-1R RRAM 4kbits arrays manufactured either with amorphous or polycrystalline HfO2 in terms of performance, reliability, Set/Reset operations energy requirements, intra-cell and inter-cell variability during 10k Set/Reset cycles is reported. Polycrystalline array shows higher current ratio, lower switching voltages, lower power consumption, minor endurance degradation and higher overall yield than amorphous array. The drawbacks are represented by the higher Forming voltage, the larger read current distribution after Forming and the higher Reset voltage dispersion

RRAM Reliability/Performance Characterization through Array Architectures Investigations

The reliability and performance characterization of each non-volatile memory technology requires the thorough investigation of dedicated array test structures that mimic the real operations of a fully functional integrated product. This makes no exception also for emerging non-volatile memories like the Resistive Random Access Memory (RRAM) concept. An extensive electrical characterization activity performed on test vehicles manufactured in a CMOS backend-of-line process allowed the first glance estimation of operation modes and reliability threats typical of this technology. In this paper, it is provided a review of the most important issues like forming instabilities, optimal set/reset operation finding, and read disturb to provide a guideline either for a further technology optimization or an efficient algorithms co-design to handle these reliability/performance threats

Reliability and Cell-to-Cell Variability of TAS-MRAM arrays under cycling conditions

The impact of 500k write cycles on 1kbits TASMRAM arrays has been evaluated by extracting a set of characteristic parameters describing the technology in terms of cell-to cell variability and switching reliability. The relationship between switching voltages and cell resistances has been investigated in order to define the most reliable working conditions

Assessing the forming temperature role on amorphous and polycrystalline HfO2-based 4 kbit RRAM arrays performance

The impact of temperature during the forming operation on the electrical cells performance and the post-programming stability were evaluated in amorphous and polycrystalline HfO2-based arrays. Forming (between − 40 and 150 °C), reset and set (at room temperature) operations were applied using the incremental step pulse with verify algorithm (ISPVA). The improvements achieved on the forming operation in terms of time and voltages reduction do not impact the subsequent reset/set results. ISPVA perturbations in LRS/HRS current distributions are almost negligible after the first reset/set operation. In this study the best improvement in forming operation in terms of yield, voltage values and cell-to-cell variability is achieved in polycrystalline samples at 80 °C

Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

The forming process, which corresponds to the activation of the switching filament in Resistive Random Access Memory (RRAM) arrays, has a strong impact on the cells’ performances. In this paper we characterize and compare different pulse forming techniques in terms of forming time, yield and cell-to-cell variability on 4 kbits RRAM arrays. Moreover, post-forming modeling during Reset operation of correctly working and over formed cells has been performed. An incremental form and verify technique, based on a sequence of trapezoidal waveforms with increasing voltages followed by a verify operation that terminates when the expected switching behavior has been achieved, showed the best results. This procedure narrows the post-forming current distribution whereas reducing the Reset switching voltage and the operative current. These advantages materialize in a better control of the cell-to-cell variability and in an overall time and energy saving at the system level

Automated characterization of TAS-MRAM test arrays

In this work the characterization results of 1kbit TAS-MRAM arrays obtained through RIFLE Automated Test Equipment of 1Kbit array are reported. Such ATE, ensuring flexibility in terms of signals and timing, allowed evaluating hysteresis and to perform 50k write cycles in a very limited time, getting a first insight on TAS-MRAM arrays performance and reliability

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures